The present invention relates to image compression, and particularly, the present invention teaches a method for performing a one-dimensional Discrete Cosine Transform (1D DCT), and a one-dimensional Inverse Discrete Cosine Transform (1D IDCT) using parallel processor architectures, such as Single Instruction Multiple Data (SIMD), Multiple Instruction Multiple Data (MIMD), Very Long Instruction Word (VLIW) and associative processor architectures.
Image compression is used in the transmission of digitized images over communication networks to reduce the amount of data in the image while maintaining as high degree of fidelity to the original image. In addition to reducing the amount of data, the goal of sustaining a fast frame rate in the compression and decompression processes has become a major objective for designers and programmers of digital signal processors and other fast processing architectures. Image compression is a central function in digital still cameras, digital camcorders, color printers and scanners and multimedia.
The present invention teaches a fast method for performing a 1D DCT and a 1D IDCT. The teachings of the present invention can be used to accelerate many DCT-based compression algorithms, such as those defined by the Joint Photographic Experts Group (JPEG) for still images, and by the Moving Picture Experts Group for video images (e.g., MPEG-2 and MPEG-4).
The 1D DCT transforms a set of points in the spatial domain to the frequency domain. The 1D DCT is performed on an array of N pixel values, and it yields an array of N frequency coefficients. The following equation shows an eight-point 1D DCT formula suitable for JPEG: ##EQU1##
Reconstructing the compressed image requires the inverse DCT (IDCT), the formula for which is given below: ##EQU2##
In both formulae, C(u)=1/.sqroot.2 for u=0; and C(u)=0 for u&gt;0. s(x) is the 1D sample value; and S(u) is the 1D DCT coefficient.
In light of the widely recognized need for fast implementations of DCT-based compression and decompression, it would be highly advantageous to have a method for implementing the 1D DCT and 1D IDCT that reduces the number of mathematical operations executed, as this reduces execution time.
Associative processor architecture enables performing logical and mathematical operations between a plurality of vectors in SIMD fashion. The advantages of associative processing will not be recounted here in the interest of brevity. Reference is made to the parent application, U.S. patent application Ser. No. 08/353,612, in which the advantages are discussed. In light of the advantages of associative processing disclosed in the referenced application, and in light of the widely recognized need for fast implementations of DCT-based compression and decompression, it would be highly advantageous to have a method for implementing the 1D DCT and 1D IDCT on an associative processing array and capable of sustaining a fast frame rate. Many additional benefits of the method disclosed will become apparent in the disclosure below.